The invention relates to an improvement in a data processor using a semiconductor logic circuit or element which has a register file and an arithmetic logic circuit both provided on one chip.
Recently, rapid development of LSI (Large Scale Integration) technology has succeeded in reducing the cost of data processors using such LSIs. Because inexpensive LSIs are available readily, it has been proposed to assemble such LSIs into a data processor assigning various functions to the LSIs and operate them systematically in the data processor thus assembled. One of the proposals employs LSIs as semiconductor logic circuit elements (hereinafter referred to as microprocessors) for central processing units (CPUs) of the data processor which are operated in accordance with software or firmware instructions. One such microprocessor is commercially available as an AM 2901A 4-bit slice microprocessor manufactured by Advanced Micro Devices Inc.
FIG. 1 is a block diagram of a conventional arithmetic control unit 10 using the microprocessors. The arithmetic control unit 10, constituted by four 4-bit slice microprocessors includes a register file 12 a Q register 13, a selector 14, an arithmetic logic unit 15, a multiplexer 16 and a shifter 17, and is capable of effecting 16-bit processing. The register file 12 is a 2-part random access memory (RAM) and the Q register 13 is used as a working register. The selector 14 additionally included in the unit 10 is provided with five input terminals for receiving data A and B from the register file 12, data Q outputted from the Q register 13, data D on a data input bus, and data U outputted from another working register (not shown). The selector 14, when receiving such input data, supplies two outputs to the arithmetic logic unit 15 (ALU). The ALU 15 performs arithmetic operations on the data from the selector 14 and supplies the result of the operations to the multiplexer 16. The multiplexer 16 selects data either from the register file 12 or the ALU 15. The data selected by the multiplexer 16 is outputed on an output data bus Y. The shifter 17, which is connected between the ALU 15 and the register file 12, shifts and rotates 32-bit data when both the register file 12 and the Q register 13 are used and shifts and rotates 16-bit data when only the register file 12 is used. The construction of the microprocessor as mentioned above is disclosed in "The AM2900 Family Data Book", 1976, published by Advanced Micro Devices Inc., Sunnyvale, Calif., and accordingly, is not described further here.
When all the registers in the register file 12 are used as general registers, they are accessed using the operand field R.sub.1 and X.sub.1 of an external instruction register 1. When some of the registers of file 12 are used as general registers and the remaining ones as working registers, access to the register file 12 is made by using the operand field R.sub.1 or X.sub.1 of the instruction register 1 and the register designation field source S.sub.1 or destination D.sub.1 of a microinstruction register (.mu.DR)2 which stores microinstructions. In this case, either the operand field R.sub.1 or X.sub.1 of the instruction register 1 and either designation field S.sub.1 or D.sub.1 of the microinstruction register 2 are selected by selectors 3 and 4 to access the register file 12. Specifically, the output of the operand field R.sub.1 and X.sub.1 of the instruction register 1 specifies an address of the register file 12 used as a general register and the output of the register designation field S.sub.1 or D.sub.1 of the microinstruction register (.mu.DR)2 specifies an address of the register file 12 used as a working register. In other words, in the construction of the conventional device described above, combination circuits such as selectors 3 and 4 are connected between the register files 12 disposed within the control unit 10, and the instruction register 1 and the microinstruction register 2 both disposed exteriorly of the control unit 10. Because of such a construction, the time to access the selectors 3 and 4 lengthens each microstep and thereby an instruction execution cycle. The solution of this problem would speed up data processing. The longest processing time in a data processor of the microprogram controlled type is taken for the execurtion of a microinstruction which inbstructs the ALU 15 to perform an arithmetic operation on the contents of a register of the register file 12 specified by the register designation fields (S.sub.1 and D.sub.1) and load the result of the operation into the register of the register file 12 designated by the register designation field D.sub.1. In such a data processor, the time for processing the longest microinstruction must be regarded as one machine cycle. As a consequence, if the time for processing the microinstruction is shortened, data processing speed could be considerably improved.